1. Field of the Invention
The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature.
2. Art Background
In high-frequency integrated circuits which utilize field-effect transistors, a bias stabilization circuit which maintains current stable is indispensable because high-frequency small-signal characteristics of field-effect transistors are determined largely by the current. Thus, many bias stabilization circuits which make drain currents stable have been proposed and used to minimize the current variation due to not only the variations of device characteristics which occur during manufacturing process, but also the variations of device characteristics due to the variations of operating temperature. Three of them are most representative methods which we will describe here referring to the figures.
FIGS. 1 to 3 are circuit diagrams of the prior art bias stabilization circuits.
FIG. 1 is a circuit diagram of a voltage feedback bias stabilization circuit which stabilizes the drain current by a negative feedback of the output voltage to the input stage.
The gate voltage of the amplification transistor 101 is supplied by the drain voltage of the amplification transistor 101 divided by resistors 111 and 112. If the current tends to increase due to the characteristic variations of the amplification transistor 101, then voltage drop at the load resistor 121 increases. The output voltage thus drops resulting in decrease of voltage at the gate of the amplification transistor 101 which in turn decreases the drain current of the amplification transistor 101. As a result of these operations, the variation of the drain current is reduced. This type of stabilization has a drawback that the amplification gain is decreased because the bias circuit is connected in parallel with the load resistor.
FIG. 2 is a circuit diagram of a current feedback bias stabilization circuit which stabilizes the drain current by a negative feedback of the drain current variations of the amplification transistor 201 to the gate voltage. The gate voltage of the amplification transistor 201 is fixed to a certain voltage by divide resistors 211 and 212. If the current tends to increase due to the characteristic variations of the amplification transistor 201, then the voltage drop across the resistor 213 connected in series with the source increases. Thus the source voltage increases while the gate voltage is maintained constant. As a result, the gate-source voltage decreases to reduce the current. This has an effect of the reduction of the variations of the drain current. This kind of stabilization circuit has a drawback that, in order to prevent decrease of the amplification gain, a large capacitor 214 has to be connected to the source in parallel with the bias stabilization resistor 213, taking much area of the integrated circuit. Also, output power handling capacity is reduced because of the DC voltage drop at the bias stabilization resistor 213.
FIG. 3 is a circuit diagram of the current mirror type bias circuit which, unlike the above mentioned feedback circuits, has a bias circuit outside of the amplification circuit, from which the gate voltage of the amplification transistor is supplied. A resistor 342 for determining the current and the transistor 341 for reference voltage generation are connected to the power supply in series. The gate voltage of the reference voltage generation transistor 341 is then supplied to the gate of the amplification transistor 301. The drain current of the amplification transistor 301 can be easily determined by the ratio of gate width between the reference voltage generation transistor 341 and the amplification transistor 301. For this circuit to be operated properly, it is necessary that the drain-source voltage of the reference voltage generation transistor 341 should be higher than the saturation voltage (about 1 V). The circuit shown in FIG. 3, however, operates at the drain-source voltage of within 0.3 V and 0.4 V, so it has inferior stability to the variations of device parameters.